The advancement towards miniaturization of technological devices has driven modern semiconductor fabrication technology into the sub-nano features. As dimensions continue to decrease, new challenges are encountered. In particular, parasitic capacitance in transistors have increased, resulting in decreased performance. In addition, capacitance coupling between metal lines in back-end-of-line (BEOL) processing has similarly increased. Increased coupling capacitance reduces signal transmission speed as well as signal integrity.
The present disclosure is related to reducing patristic capacitance in transistors as well as coupling capacitance in metal lines.